| Term | Definition |
|---|---|
| ALU | Arithmetic Logic Unit |
| CQ | Command Queue |
| EEW | Effective Element Width |
| IF | Instructions Fetch |
| LMUL | Vector register group multiplier |
| LSU | Load-Store Unit |
| MAC | Multiply-Accumulate |
| NNE | Number of Executing Elements |
| PMT | Permutation unit |
| RAW | Read-After-Write |
| RDT | Reduction unit |
| ROB | Reorder Buffer |
| RVS | RISC-V Scalar core |
| RVV | RISC-V Vector engine |
| SEW | Selected Element Width |
| SIMD | Single instruction, multiple data |
| VCSR | Vector Control and Status Registers (vl, vtype, vstart) |
| VRF | Vector Register File |
| XRF | X (scalar) Register File |
| WAR | Write-After-Read |
| WAW | Write-After-Write |
| µop | Micro-operation |